A Multistage Heuristic Tuning Algorithm for an Analog Silicon Neuron Circuit

DOI

10.2991/jrnal.2017.4.1.13How to use a DOI?

Keywords

neuromorphic engineering, analog VLSI, silicon neurons

Abstract

This research looks at an ultra-low power subthreshold-operated silicon neuron circuit designed with qualitative neuronal modeling. One technical challenge to future implementation of such circuits is parameter tuning — a problem stemming from temperature sensitivity of subthreshold-operated MOSFETs and the uniqueness of individual circuits in a neuronal network due to transistor variation. This research proposes a fully automated parameter tuning algorithm that combines two heuristic approaches to search for appropriate circuit parameters over a range of temperatures. The algorithm can tune the circuit to behave as a Class I or Class II neuron.

Copyright

© 2013, the Authors. Published by Atlantis Press.

Open Access

This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

Download article (PDF)

TY  - JOUR
AU  - Ethan Green
AU  - Takashi Kohno
PY  - 2017
DA  - 2017/06/01
TI  - A Multistage Heuristic Tuning Algorithm for an Analog Silicon Neuron Circuit
JO  - Journal of Robotics, Networking and Artificial Life
SP  - 58
EP  - 61
VL  - 4
IS  - 1
SN  - 2352-6386
UR  - https://doi.org/10.2991/jrnal.2017.4.1.13
DO  - 10.2991/jrnal.2017.4.1.13
ID  - Green2017
ER  -