Implementing EW Receivers Based on Large Point Reconfigured FFT on FPGA Platforms
- DOI
- 10.2991/ijcis.2011.4.6.3How to use a DOI?
- Keywords
- Digital receivers, field programmable gate array (FPGA), fast Fourier transform (FFT), large point reconfigured, signal processing system.
- Abstract
This paper presents design and implementation of digital receiver based on large point fast Fourier transform (FFT) suitable for electronic warfare (EW) applications. When implementing the FFT algorithm on field-programmable gate array (FPGA) platforms, the primary goal is to maximize throughput and minimize area. This algorithm adopts two-dimension, parallel and pipeline stream mode and implements the reconfiguration of FFT's points. Moreover, a double-sequence-separation FFT algorithm has been implemented in order to achieve faster real time processing in broadband digital receivers. The performance of the hardware implementation on the FPGA platforms of broadband digital receivers has been analyzed in depth. It reaches the requirement of high-speed digital signal processing, and reveals the designing this kind of digital signal processing systems on FPGA platforms. Keywords: digital receivers, field programmable gate array (FPGA), fast Fourier transform (FFT), large point reconfigured, signal processing system.
- Copyright
- © 2011, the Authors. Published by Atlantis Press.
- Open Access
- This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).
Cite this article
TY - JOUR AU - He Chen AU - Xiujie Qu AU - Yuedong Luo AU - Chenwei Deng PY - 2011 DA - 2011/12/01 TI - Implementing EW Receivers Based on Large Point Reconfigured FFT on FPGA Platforms JO - International Journal of Computational Intelligence Systems SP - 1131 EP - 1139 VL - 4 IS - 6 SN - 1875-6883 UR - https://doi.org/10.2991/ijcis.2011.4.6.3 DO - 10.2991/ijcis.2011.4.6.3 ID - Chen2011 ER -